Programmable logic devices, such as for example a field programmable gate array (FPGA) or a complex programmable logic device (CPLD), often include general purpose input/output circuits that are programmable to support numerous input/output interface standards. The input/output interface standards typically have a wide range of requirements that must be satisfied.
As an example, some types of input/output interface standards (e.g., double data rate (DDR) synchronized dynamic random access memory (SDRAM) interface standard) require a delay inserted in the data path or the clock path to reliably capture the data. A typical delay cell that is utilized to provide a signal delay may provide a delay that varies widely over process, voltage, and temperature. The delay range, for example, may be 2:1 to more than 3:1 for the maximum to minimum delay ratio. For a stringent input/output interface standard that requires a large delay on the data path or the clock path and also a narrow valid data window, the typical delay cell may fail to meet the requirement.
One type of delay cell, an analog delay cell, utilizes a feedback path to reduce the amount of variation due to process, voltage, or temperature fluctuations. Analog delay cells, however, often suffer from various limitations, such as noise susceptibility, delay precision limitations, or process refinement uncertainties.
Additionally, a path delay (e.g., clock injection delay) may be difficult to cancel or track with analog delay cells, because the path delay may vary greatly based on the size of a device (e.g., within a device family). Furthermore, the path delay may vary with process, voltage and temperature (e.g., due to transistor sizing, transistor type, type of delay such as resistor-capacitor vs. transistor delay ratio) in ways that make it difficult for analog delay cells to completely compensate. As a result, there is a need for improved techniques for implementing signal delays in programmable logic devices.